1) Field of the Invention
The present invention relates to a fabrication method of a semiconductor integrated circuit device, particularly to a technique effective when applied to formation of inlaid interconnects by chemical mechanical polishing (CMP) and more particularly to a method for cleaning Cu containing metal after a chemical-mechanical polish (CMP) process.
2) Description of the Prior Art
In a technique for forming interconnections comprising semiconductor integrated circuit devices, semiconductor devices, electronic circuit devices and electronic devices, a conducting film, such as, for example, aluminum or tungsten, is deposited over an insulating film and is patterned by ordinary photolithography and dry etching.
However, in this interconnection forming technique, as devices and interconnections comprising semiconductor integrated circuit devices become finer, interconnection resistances are largely increasing, interconnection delays are occurring, and a limit is being reached to further performance improvements of the semiconductor integrated circuit devices.
In recent years, an interconnection forming technique known as the Damascene method has been developed. This Damascene method may be broadly distinguished into two types, i.e., the Single Damascene method and the Dual Damascene method.
In the single damascene method, after forming an interconnection slot in an insulating film, for example, a main conducting layer for forming interconnections is deposited over this insulating film and in the interconnection slot, and an embedded interconnection in the interconnection slot is formed by polishing this main conducting layer by, for example, CMP (Chemical Mechanical Polishing), so that it is left only in the interconnection slot.
In the Dual Damascene method, after forming a connecting hole to connect with the interconnection slot and a substrate interconnection in the insulating film, a main conducting layer for forming interconnections is deposited over this insulating film and in the interconnection slot and connecting hole, and an embedded interconnection in the interconnection slot and the connecting hole is formed by polishing this main conducting layer by, for example, CMP (Chemical Mechanical Polishing), so that it is left only in the interconnection slot and connecting hole.
In both methods, a material such as copper or the like is used as the material of the main conducting layer of the interconnections from the viewpoint of improving the performance of the semiconductor integrated circuit device. Copper has the advantage that, compared to aluminum, its resistance is lower and its permitted current for reliability is more than two orders of magnitude higher. Hence, the film can be made thinner to obtain the same interconnection resistance, and the capacitance between adjacent interconnections can be reduced.
However, copper interconnects used in CMP processes have problems.
Relevant patent and technical literature are as follows.
U.S. Pat. No. 6,764,950B2 Noguchi, et al. and US 20010030367 A1—Noguchi, Junji; et al. Oct. 18, 2001—Semiconductor integrated circuit device and fabrication method for semiconductor integrated circuit device.
US 20040152333 A1—Zhao, Larry; et al. Aug. 5, 2004—Dielectric barrier layer for a copper metallization layer having a varying silicon concentration along its thickness.
U.S. Pat. No. 6,764,951 van Ngo Jul. 20, 2004—Method for forming nitride capped Cu lines with reduced hillock formation.
“Adhesion Quantification of Pos-CmP Cu to amorphous SiN passivation by NanoIndentation”, by Vella et al., pp. Q6.1.1Q.6.1.6, discusses Cu treatments.
U.S. Pat. No. 5,913,144 Nguyen, et al.—Oxidized diffusion barrier surface for the adherence of copper and method for same.